Recent developments in memory applications, such as mass storage, code memory, and other multimedia applications increasingly require memory devices with higher density. Mass storage applications may include memory cards (for example, for mobile computers), solid-state memory (for example, sturdy and/or reliable storage disks), digital cameras (for recording still or moving images and sound), and voice or audio recorders for recording near CD quality sound).
Code memory applications may include basic input/output systems (BIOS) or network applications (for example, memory in a personal computer, other terminal, router, or hub), telecommunications applications (for example, switches), mobile phone applications (for example, codes and/or data), and other electronic handheld information device applications (for example, codes and/or data for personal digital assistants (PDA), palm operating systems (POS), or personal communications assistants (PCA)).
Generally, mass storage applications use memory that is lower cost, higher density, and/or has better program/erase (P/E) cycling endurance, while code memory applications have faster random access and/or are executable in place (XIP).
Related art memories may include dynamic random access memory (DRAM), static random access memory (SRAM), and non-volatile memory (NVM). Non-volatile memory may include mask read only memory (ROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), flash memory (for example, flash erase EEPROM), and ferro-electric memory. Non-volatile memory does not lose data when power is lost, but generally does not permit random access and is generally slower than volatile memory.
Flash memory may be formed by a combination of erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM). Flash memory may be NAND or NOR flash memory. Erase and program operations may be performed in a flash memory by the application of different voltages to each flash memory cell.
NAND flash memory may include a string of serially connected cells (for example, 16 cells may make up a string). The string may include one or more string select transistors. NAND flash memory may have a relatively small “on” cell current and hence, relatively slow sensing time (for example, 10-25 ms). NAND flash memory may perform a read operation by simultaneously sensing and latching a page unit (for example, 512 bytes) to a page buffers. NAND flash memory may read data from a page buffer latch at a relatively high speed (for example, 50 ns).
NAND flash memory may perform program and/or erase operations by tunneling (for example, Fowler-Nordheim (F-N) tunneling). A program operation may include a relatively fast serial data loading to a page buffer (for example, 50 ns), where cells (for example, 512 bytes) are simultaneously programmed. An erase operation may be a block unit erase where a number of pages (for example, 32 pages of 16 K bytes cells) are simultaneously erased.
Reliable F-N tunneling may be performed at approximately 10 mV/cm. which may result in lower power consumption, lower temperature dependence, more uniform program/erase operation, and/or easier device/voltage scaling.
NAND flash program operation may utilize a coupling between a gate and a channel. For example, a cell to be programmed may have a larger voltage difference between the gate and the channel than a cell not to be programmed. NAND flash program operation may also utilize a threshold voltage distribution, an example of which is shown in FIG. 1. FIG. 1 illustrates the relationship between a word line voltage Vword line (for example, 0V), a read voltage Vread, and a cell voltage distribution Vth of an unprogrammed (or erased) cell and a programmed cell. In FIG. 1, Y-direction represents the threshold voltage of the storage cell and X-direction represents the number of cells at a certain threshold voltage.
Conventionally, a cell voltage distribution Vth has been controlled by an increment step pulse program (ISPP). Example ISPPs are shown in FIGS. 2a and 2b. FIG. 2a shows an example, related art ISPP, where the pulse width and amplitude remain the same. As shown, a voltage V0 (for example, 18V) is applied during a program period (for example, 30 μs) and another voltage V1 (for example, 1.2V) is applied during a verify period (for example, 5 μs). FIG. 2b shows an example, related art ISPP, where the pulse width remains the same, but the amplitude is varied. As shown, a voltage V0 (for example, 15V) is applied during a first program period (for example, 30 μs) and incremented (by for example, 0.5 V) for each successive program period until a final voltage Vn (for example, 19V) is reached. Another voltage V1 (for example, 1.2V) is applied during each verify period (for example, 5 μs). In both FIGS. 2a and 2b, the total duration is around 250 μs. The cell voltage Vth variation and the number of cycles for FIG. 2b are advantageously smaller than for FIG. 2a. 
FIG. 3 illustrates a related art over-programming problem. If the cell threshold voltage Vth is higher than Vread, a normal read operation for a NAND cell string may not be performed properly. Related art procedures exist to prevent over-programming during ISPP.
Related art procedures also utilize a flag or other mark to indicate that a normal cell program operation has been properly completed. A flag or other mark is used due to the relatively long programming time (around 250 μs as indicated above) for a NAND flash memory. During this relatively long programming time, a power-off or other similar interruption may occur. The flag or other mark is used to confirm that the program operation was completed. FIG. 4a illustrates an example where the flag or other mark (for example, a confirm mark) was completed and FIG. 4b illustrates an example where the normal programming and/or the flag or other mark were not completed.
In related art procedures, when the normal cell program operation or operations are performed, a determination is made as to whether the operation is complete, and if so, the flag or other mark is written. The flag or other mark may be written in a spare cell region of memory.
FIG. 5a illustrates a related art normal cell program and confirm cell program, as well as, a related art normal cell program time and confirm cell program time. As shown, both the related art normal cell program time and the confirm cell program time include loops of one program period and one verify period. FIG. 5b illustrates an example, related art memory location to which the normal cell program and the confirm cell program may be written. As illustrated in FIG. 5b, for the cell program write:
1 page/1 program time=512 byte/1 program time=4 k bit/250 μs (200 μs˜300 μs)=16.4 bit/1 μs.
For the confirm mark write:
1 bit/1 program time=1 bit 250 μs=0.004 bit 1 μs.
As is clear from the above, the confirm mark write is less efficient than the cell program write.